74HC164 and 74HC595 comparision

74HC595

The 74HC595 is a high speed 8-BIT SHIFT REGISTERS with OUTPUT LATCHES (3-STATE) fabricated with silicon gate CMOS technology. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register.

The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

74HC164

The 74HC164 is an 8-bit serial-in/parallel-out shift register.

The device features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH transitions of the clock (CP) input. A LOW on the master reset input (MR) clears the register and forces all outputs LOW, independently of other inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

 

 

74HC595 VS 74HC164

74HC595 is faster than 74HC164 and works on lower voltage.

To be more specific:

74HC595 has a latch, so the output can remain unchanged during the shift; 74HC164 has no latch, so it changes every time a shift clock is generated. This is the biggest difference between the two.

74HC595 uses special Q7 pin to realize multi-chip cascade; 74HC164 directly uses output pin Q7 to cascade.

74HC595 has enable OE, when OE is invalid, the output pin is high impedance; while 74HC164 has no enable pin.

The reset of 74HC595 is for the shift register. If you want to reset the LATCH register, you must load the shift register content into the latch register on the rising edge of ST_CP; that is to say: 74HC595 reset is synchronous, 74HC164 reset is asynchronous, and so the reset of 74HC164 is easier.

74HC164 has a corresponding 74HC165 parallel-to-serial chip.